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LBC5

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1. LBC5 PDK 2015.12.22 Release (Dec'15)

1.1. CDK (4.6.b.30)

  1. DONE Net purposes updated for Dynamic pcell abstraction 1 Updated DNWELL,PMOAT,NMOAT,POR nets 1 updated laff files, display files 1 blockage purpose Datatype stream number added in lbc5.layermap file
  2. DONE Pcell update- RES_METDCU 1 Sheet rho updated to 0.0057 from 0.0063

1.2. Rules

1.2.1. Assura DRC
  1. DONE Added safety check for presence of slot layers or holes in metal or poly resistor body

1.2.2. Assura LVS
  1. DONE Updated METDCU sheetrho value per PCD 5.0. This will change the calculated resistance of METDCU resistors
  2. DONE Replaced tiMeasureLdd macro with sjMeasureLdd macro to fix a bug in shared mos parameter calculation with mi>2

1.2.3. Assura XOR
  1. DONE Added following 'net' layer purposes for comparison: 1 DONE POR, NMOAT, PMOAT, DNWELL

1.2.4. VER
  1. DONE (drc) Sync'ed up rule 17S8 to report errors similar to Assura DRC
  2. DONE (drc) Added safety checks to report slot layer/holes on metal, poly resistor body
  3. DONE (wpg) Made SSA on 45 degree metal as default
  4. DONE (wpg) Closure of Test pad openings is not enabled when SCRIBE rpp is set
  5. DONE (wpg) Added warnings to report DNWELL & DWELL layers do not support 5x reticle scale in CFAB

1.2.5. WPG
1 DONE Difflay Updates 1 Added following layers for XOR checks using difflay: RCXPROBE (opt7,8) 1 Corrected checking for SCRFILL and SCRCVR layers

  1. DONE PG deck updates 1 Made SSA on 45 degree metal as default 1 Closure of Test pad openings is not enabled when SCRIBE rpp is set 1 Added warnings to report DNWELL & DWELL layers do not support 5x reticle scale in CFAB

1.3. QRC

  1. DONE Following updates done for all metdcu flows (ie; metdcu_2m, metdcu_3m, metdcu_4m) as per PCD v5.0:
    1. Updated METDCU & POR resistance values in ictfiles
    2. Added temperature co-efficients for METDCU
    3. Regenerated QRC techfiles
    4. METDCU sheetrho changed
      From
      0.0053(min), 0.0063(typ), 0.0073(max)
      To
      0.0043(min), 0.0057(typ), 0.0071(max)
    5. POR via resistance changed
      From
      0.320(min), 0.320(typ), 0.320(max) To: 0.120(min), 0.220(typ), 0.320(max) 1 DONE meshR.defs file removed from all process flavors and corners 1 DONE Added meshR.defs file in the assura directory as per new EDA spec
1.3.1. Note
1 DONE A special QRC corner (minC_minvia_EMIR_Ronly) for each metal stack is supported for R only extraction for VPS (EMIR) 1 This special QRC corner will extract diffusion resistance which will be in parallel with MET1 connected through CONT resistance. 1 Users should NOT use this corner for anything other than QRC extraction for R only EMIR runs. This is because you will be double counting certain capacitances. 1 Users should use the regular QRC corners for all other QRC extraction.
  1. To use this corner:
    1. In the Quantus QRC fill form, provide the path in the 'Setup dir' field
    2. After the above change you can run QRC for EMIR/VPS as normal BUT, once you have completed QRC for EMIR, please re-set the 'Setup Dir' field in the form (remove the special entry) so that you do not accidently run this special QRC corner for your other QRC related simulations.

1.4. R3D

1 DONE r3d_qrc.map file updated to align with the METDCU VIATOP 1um values 1 DONE VIATOP 1um values changed from 0.39,0.32,0.32 (max,typ,min) to 0.32.0.22.0.12(max,typ,min) 1 DONE stream_layer_map file updated to add net purpose updates and RCXPROBE7/8 layers

1.5. Models

1 DONE Release to go to the new style asserts 1 DONE NCH_JFET_HV5 Final 5.10 : Update raw model based on silicon x2618. PCD version is unchanged. jagva*.nch_jfet_hv5 1 DONE First release of sub-circuit based asserts using latest format, version 3.1. Slight update to the reliability_asserts.scs file and addition of reliability aging models
  1. For complete documentation and offsite downloading see: http://msp.dal.design.ti.com/sml/webdoc/lbc5/msp/2015.12.08.html

1.6. DIGLIB

1.6.1. DONE msl730 : r1.2.0

1 CADENCE LIBRARY 1 vams and verilog views added for all cells 1 vams, verilog and symbol views added for udp cells

1 PAL

    1. vams_2pin and verilog_pg_2pin directories added with
    2. models for all cells inside them.

1 ITDB

    1. itdb data provided for 2m, 3m and 4m metal systems
      1. For more information on compiling .libs refer the FAQ http://www.india.ti.com/~mdcl/FAQ/doc/liberty_compilation.html

1.6.2. DONE tla950 : r2.0.0

1 CADENCE LIBRARY 1 vams and verilog views added for all cells 1 vams, verilog and symbol views added for udp cells

1 PAL

    1. vams_2pin, vams_3pin, verilog_pg_2pin and verilog_pg_3pin directories have been added with models of 215 cells inside each of them. These directories are placed parallel to verilog directory

1 ITDB

    1. 3layer and 4layer itdb data provided for 2pin and 3pin configurations

1 vdio

    1. techlef support for metdcu_2m provided The information about porting the routed design from VDIO to Cadence is available at: http://www.india.ti.com/~mdcl

1.7. ESDLIB

1.7.1. ESDLIB : 2015.12.14
1 new ESD cells have been added to the ESD library. These ESD cells are compatible with the latest packaging rules enabling them to be placed under the bondpad RELATED DOCUMENTATION: SiTD ESD Lab Web Page: http://msp.dal.design.ti.com/sml/esd.html Contact: Aravind Appaswamy a-appaswamy@tiPLEASENOSPAM.com

1.7.2. Sparks : 2015.10.28
1 Sparks techfiles are updated with V6 version of techfiles. The techfiles are compatible with spectre only netlisting. ESD SPARKS DEVELOPER: Byung-Jin Choi, mailto:byung-jin.choi@tiPLEASENOSPAM.com

1.8. MISC

1.8.1. Lbc5_copper 2015.12.14
  1. PAD schematic tiRefLib capacitor C13 did not has unit, Updated PAD schematic to have unit [1e-12] for the cap C13. This was done to resolve convergence issues in certain [parallel PAD instance] scenario
  2. layoutB is created in BallShearPIORCD pcell layout to add BOND layer as per the latest DR rule

2. LBC5 PDK Next Release (March'16)

3. Previous Release Notes and Archive PDK twiki pages

4. Comments

  • Diff PDK Flow:
    diffPdk.PNG

LBC9

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1. CDK Checklist

1.1. New component addition

  1. Sample Layout -- run DRC & feedback generic rule violations to PI, PV
  2. Create CDF (Make auLVS as needed by LVS)
  3. Symbol (auLVS, ivpcell)
  4. Schematic
  5. Send Netlist to SML
  6. PCELL (Need samples for mi>1,w+,L+ ..)
  7. QA PCELL (Taguchi Dep, Need DRC Rules)
  8. Add PERF Test Line (DRC,LVS, QRC,SIM, NC..)
  9. Add PCCB FB (can be done now)
  10. Test VXL (Need PCELL with Pins)
  11. Test SimQC (need Stage Models to be ready)
  12. Test Equations (Parasitics: geometry -NC: need QRC ready)
  13. lbc9 vs. lbc9_ext syncup
  14. cph.lam update

1.2. Existing component update

  1. CDF Update
  2. PCELL Recompile If Any
  3. Subcircuit Mod. If any
  4. Test VXL
  5. test for JUMP migration
  6. QA Cell Update
  7. Add FB PCCCB Entry
  8. Test Equations (Parasitica: geometry -NC: need QRC ready)
  9. lbc9 vs. lbc9_ext syncup
  10. cph.lam update

2. LBC9 Service PDK1.6 (Jan'16)

2.1. Diglib

  1. Expansion of MSL710

2.2. Models

  1. Strawman models for #115, 116, 135
  2. Silicon based model for #401
  3. Update of all poly resistor models (200, 201, 202, 204, 206, 209) with 1/f noise and updated mismatch coefficient

2.3. CDK

  1. DONE Change the min L to align with PCD for #115 and #116 - Johnny
  2. DONE Align the QA cells for #115 and #116 (layout_DRC & layout_LVS) - Charles
  3. Add new 5V natural NMOS #135 to PDK (symbol, schematic, layout)
  4. Add new NCH_1V8_SBLK_401 (symbol, schematic, layout)
  5. DONE CVF - The SCRIBE_SEAL in the std MV flow (MET3_1UM, 1U VIATOP, METTOP) seems to work ok with the exception when “LOCOS for low Q*R LDMOS [LOCOS]” choice is included – the SCRIBE_SEAL does not show up.
  6. Review symbols pcells for components (MOS, DEMOS, etc) to verify thin/thick Gox line is evident.

2.4. LVS

  1. Change the min L to align with PCD for #115 and #116
  2. Add LVS for new 5V natural NMOS #135
  3. Add LVS for new NCH_1V8_SBLK_401

2.5. DRC

  1. Change the min L to align with PCD for #115 and #116
  2. Add seed and device specific rules for new 5V natural NMOS #135
  3. Add seed and device specific rules for new NCH_1V8_SBLK_401

2.6. R3D

  1. Add new components #135, 401
  2. Any change for #115 & 116

2.7. QRC

  1. Ensure that QRC passes for #115, 116, 401, 135

3. LBC9 Secure/Production PDK1.7 (Apr'16)

3.1. Diglib

  1. Release of 5V low cost library (with NLDD2 5V NMOS + no-PLDD2 5V PMOS)

3.2. Models

  1. Add silicon models for SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443,
  2. Fix diffusion resistor model for #207 to replace snw_pepi diode with nsd_spw diode
  3. Replace 511 type models and model cards with 288 (currently 511 is still used for 230 and 232 caps)
  4. Silicon model for DEP_122
  5. Silicon model for #144 & 146
  6. silicon models for diodes 287, 288, 289
  7. New model for #230 with Cap density quoted at 1.8V.
  8. 290 component -- for nbl2psub & Vxx both set to V08, and only toggle being LV vs. MV, different NBL-pepi diode models are called which have different characteristics. LV is silicon based diode (from CMOS silicon data) and MV is strawman diode #516 [J]
  9. Add RES_METTOP as a component (SVA request: David Zakharian)
  10. Asserts update for 7V LDMOS to increase the rating to 9V (pending PCD update)
  11. Strawman models for #129, 130

3.3. ESD

  1. Bosch request to provide documentation for ESD cells
  2. Handling of custom ESD cells (e.g. the one delivered to Verrazano)
  3. 5V pin protection using components without LDD2 (e.g. using #121 which do not use LDD2)
  4. Why does 2x20V_LV require PBLMV & PDRNLV when 40V NPN_LV cell does not. Why should 2x20v use 40V DEPMOS_LV?
  5. DEN_20V_MV_133 layout update in CDK -- is there an ESD solution to protect this component?
  6. Are there ESD solutions to protect the low QR LDMOS (171, 175, 177)
  7. New ESD cells using SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443,
  8. Is there ESD protection for #144 & 146

3.4. CDK

  1. See Bosch request for Voltus support -- Venu
  2. Thick copper scribe seal (18um METTOP) in both PLV & LBC9.0 -- Johnny
  3. Fix problem with auto-generated netlist check test cases for - 211, 234 (Venu)
  4. Fix the dbdpi equations in 131, 133, 139 (Barath)
  5. Routing creating short between BTWO (ISO) and SUB (PBKG) for 264 forQA_ALL layout in PDK 1.5 release.
  6. Remove wrong placements of DTDPN layer in 429 component and add missing PIN info to SUB terminal for VSR routing (Venu)
  7. Add support for #144 & 146 -- needs pcells, symbol, schem, etc, -- Barath
  8. Add SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443 (Venu/Johnny)
  9. Source side equations need to be updated to reflect the correct source side perim & area (0.6um used instead of 0.475um) due to adjustment driven by rule 22B14b for 122, 134
  10. DVRLO flags & spectre issue -- need to implement the fix proposed by EDA team [04/23/2015] -- Venu
  11. Update 230 and 232 caps and replace currently used 511 diodes with equivalent (name change only - check if model update is needed - see model section) 288 diodes, Venu's comment = Need more details here: 230 uses both 505, 511 A and Perimeter, DC and AC making total combinations of 4 diodes. It is better we define what exactly is being changed
  12. Adding a text for outside Vxx in a DT in layout & schematic
  13. poly resistor head update (per Stefan Herzer) to have offset heads -- Venu
  14. Power routing pcell -- add 3um support -- Barath
  15. PCD updates for existing #280 and 282 diodes (min area update -- wait for PCD change pending X2654 silicon) -- Venu
  16. Discuss the symbol netlabel colorr or movement to avoid confusion between node voltages vs terminal node voltages (Ref: email conversation) - Venu
  17. Std CMOS schematic equations do not match the extracted values for DBSA when butting backgate is present. Fix incorrect area/perimeter equations in schematic sub-circuit for (Johnny)
    1. 101
    2. 102
    3. 105
    4. 106
    5. 107
    6. 108
    7. 131
    8. 133
    9. 207
    10. 208
    11. 411
    12. 469
  18. Add via symbolics for wide metdcu overlap of via -- see Rex's message from 10/31/15 -- Johnny
  19. Add RES_METTOP as a component (SVA request: David Zakharian) -- Venu
  20. 40V & 80V JFET (nice to have, not a must do for PDK1.7)
  21. CVF - The SCRIBE_SEAL in the std MV flow (MET3_1UM, 1U VIATOP, METTOP) seems to work ok with the exception when “LOCOS for low Q*R LDMOS [LOCOS]” choice is included – the SCRIBE_SEAL does not show up -- Pushpa
  22. PLV updates based on X2654 learning -- TBD (all changes will be communicated by PI on 2/15/16)
  23. 1.5V high speed CMOS (#129, 130) -- Johnny
  24. DONE Fix NCH_5V_SBLK_411 subcircuit for QNPND ; Also add drain resistor in the subcircuit similar to SCRs. - Johnny
  25. We need to figure out to make "DUMMY" on layer "text" (lowercase sytem) make it to gdsii. (Scott Johannesmeyer)
  26. For all resistors, when serpentine option is chosen -> set the default/min links to 3. - Venu

3.5. DRC

  1. Add support for SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443, #144 & 146
  2. New components 1.5V high speed CMOS (#129, 130)
  3. Add 100B100* rules
  4. Add field transistor rules
  5. Metal dummy fill in cadence window
  6. Are the MRC rules available -- if so, add them to the DRC deck
  7. Adding a text for outside Vxx in a DT in layout & schematic
  8. Add RES_METTOP as a component (SVA request: David Zakharian)
  9. Check for off-grid error on pseudo poly_hv layer
  10. Add MRC rules (FB 55549, 55551, 55552)
  11. We need to update assura drc to make "DTorDEEPN_Label" stuff work the same for both DFII -and- gdsii.
  12. Fix the LDD2 to implant spacing flag methodology when more than 1 components are placed next to each other.

3.6. LVS

  1. Add support for SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443, #144 & 146
  2. New 1.5V high speed CMOS 129, 130
  3. Replace DIO_SNW_SPW_511 with DIO_SNW_SPW_288 in layout extracted simulation - pending CDK updates
  4. See Bosch request for Voltus support
  5. Adding a text for outside Vxx in a DT in layout & schematic
  6. Add RES_METTOP as a component (SVA request: David Zakharian)

3.7. R3D

  1. Add support for SCR_7V_HSD_LV_441, SCR_15V_LV_435, SCR_20V_HSD_LV_442, SCR_30V_HSD_443, #144 & 146
  2. Add RES_METTOP as a component (SVA request: David Zakharian)
  3. New 1.5V high speed CMOS 129, 130

3.8. LBC9 QC methodology

  1. Clear out the CDK related issues highlighted in the PERF [J, V, B]
    1. cdktest - Tier1: techfile sanity checks (Johnny)
    2. cdf_param_check
    3. edaspec
  2. Clear out QRC related issues highlighted in the PERF [M]
    1. edapv/edapv_new
  3. Add PIN connections for all component symbol terminals in schematic for pcells/symbols that were updated. Regenerate these QA cell(s) with VXL to highlight any issues with auto-routing of pins.
    1. Need confirmation if PIN info was added to 514 and 429 (Johnny/Venu)
  4. Regenerate QA_ALL cell with VXL to highlight any issues with auto-routing of pins.
  5. ALERT! For pcell Unit QC - refer to attachment(UnitQC_of_Pcells_Ver1.docx) at bottom of page

3.8.1. Venu
  1. PERF integration of customSimQC
  2. CMOS Pcell designer template

4. LBC9 Secure/Production PDK1.8 (Jun'16)

4.1. Models

  1. New variable width high sheet poly resistor model

4.2. CDK

  1. New variable width high sheet poly resistor model

4.3. DRC/LVS

  1. New variable width high sheet poly resistor model

5. Previous Release Notes and Archive PDK twiki pages

6. Comments

  • Diff PDK Flow:
    diffPdk.PNG

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Topic revision: r3 - 2015-12-15 - ShankarJagannathi
 
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