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"Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC', which is an enhanced interrupt controller, it enables us to route hardware interrupts to multiple CPUs, or to CPU groups." -- from (1) below. (In my words, based on a quick skim: among other things, to share and manage IRQs from multiple devices, among multiple CPUs. IIUC, this is one way IRQs are automatically assigned based on their slot position on a motherboard, but up to four IRQs may come from each slot.)

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  • () RandyKramer - 07 Aug 2002
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Topic revision: r1 - 2002-08-07 - RandyKramer
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