HongThi Tran

Working pages

1. Projects

1.1 DMA IP (70% of time)

Main Task	Estimated Time	Status	Note
1. Investigating AMBA BUS in general	2 days
2. Understanding existing AMBA BUS DMA core	3 + 1 days		1 reserved day for other tasks
3. Read more about DMA related issues and imagine the Overview Design Flow for my owner AMBA Bus DMA IP core	6 + 2 days	In progress
4. Doing specification and write a full reports	30 days + 3	In progress
5. Coding RTL (with basic feature of an AMBA BUS DMA)	30 + 5 days	not yet	will be done simultaneously with step 4 to ensure the specification in step 4 is correct
6. Upgrading the simple IP with some more required complex features	40 + 5 days	not yet
7. Comparing advantage & disadvantage between my owner core with others existing AMBA DMA cores	Belong to situation	not yet	Continue to upgare if possible
8. Designing a GUI for user select the core parameters	Belong to situation	not yet

Notes: days = working days
• : Done

1.2 Open RISC 1200 (15% of time)

1.3 Other activities (For Improve working efficiency and myself knowledge ...) (15% of time)

1.3.1 Searching for short course:

Course Name	Learn at	Fee	Learn Time	Organized by	More details
ADVANCED DIGITAL IC DESIGN	EPFL, Lausanne, Switzerland	EUR 1,900	24-28/8/2009	MEAD Education	contents More about fee
Power Management			31/8-4/9/2009		contents
High-Speed Digital Design		995euro	15-16/6/2009
Embedded Systems Week	France		11-16/10/2009	EURO TRAINING COURSE	more details
DSP for FPGAs	UK	1650 UK£	27-30/9/2009		More details]
FPGAs and Embedded Processors	UK	1350 UK£	17-19/11/2009		More details

Know more at: attach file

1.3.2. Construct a Twiki page to manage project

• In Progress.

2. Weekly Status

WW 21 (18 - 22/5/09)

• Translate HN-07's article to english version..
• Perform step 3 of DMA project (search from documents in internet, read them and tried to have an overview sign)
• Update twiki page.

WW 20 (11 - 15/5/09)

• Investigate DMA project.
• Join Hoang's SG8V1 presentation -> Understand a lot!
• Investigating Harvard, WISHBONE BUS Architecture.
• IQ Test.
• Investigating overal OR1200's architecture and CPU's verilog code.

My TWiki Links

• Sandbox - try out TWiki on your own
• HongThiTranSandbox - just for me
• ChangePassword for changing your password